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Disambiguation of "Stanisavljevic, Milos"

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Multilevel-Cell Phase-Change Memory: A Viable Technology.

, , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (1): 87-100 (2016)

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Milos Draskovic University of Stuttgart

 

Other publications of authors with the same name

Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation., , and . VLSI-SoC, page 328-334. IEEE, (2010)A Fast and Scalable Pipeline for Stain Normalization of Whole-Slide Images in Histopathology., , , , , , , , and . ECCV Workshops (6), volume 11134 of Lecture Notes in Computer Science, page 424-436. Springer, (2018)Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density., , , , and . ACM Great Lakes Symposium on VLSI, page 204-207. ACM, (2007)Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density., , and . IJCNN, page 2771-2778. IEEE, (2006)Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures., , , , and . IRPS, page 5. IEEE, (2015)Multilevel-Cell Phase-Change Memory: A Viable Technology., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (1): 87-100 (2016)A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory., , , , , , , , , and 1 other author(s). A-SSCC, page 137-140. IEEE, (2014)Selective redundancy-based design techniques for the minimization of local delay variations., , and . ISCAS, page 2486-2489. IEEE, (2010)Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth., , and . NanoNet, volume 20 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 70-75. Springer, (2009)Deep learning acceleration based on in-memory computing., , , , , , , , , and 7 other author(s). IBM Journal of Research and Development, 63 (6): 7:1-7:16 (2019)