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Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (5): 726-739 (2015)A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation., , , , , and . ISPD, page 161-168. ACM, (2016)A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (9): 1585-1598 (2019)RELAXNet: Residual efficient learning and attention expected fusion network for real-time semantic segmentation., , , , and . Neurocomputing, (2022)Methodology for standard cell compliance and detailed placement for triple patterning lithography., , , and . ICCAD, page 349-356. IEEE, (2013)Concurrent Pin Access Optimization for Unidirectional Routing., , , and . DAC, page 20:1-20:6. ACM, (2017)Self-aligned double patterning aware pin access and standard cell layout co-optimization., , , , and . ISPD, page 101-108. ACM, (2014)MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes., , , , , , , , and . ICCAD, page 7. ACM, (2016)MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction., , , and . DAC, page 52:1-52:6. ACM, (2014)Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits., , , , and . ISPD, page 55-62. ACM, (2017)