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A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.

, , , , , , and . International Journal of Parallel Programming, 27 (2): 97-109 (1999)

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A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR., , , , , , and . International Journal of Parallel Programming, 27 (2): 97-109 (1999)Low-Complexity Bypass Network Using Small RAM., , , , , and . CDES, page 153-159. CSREA Press, (2008)Prototype Implementation of a GPU-based Interactive Coupled Fluid-Structure Simulation., , , , , , and . SNPD, page 721-725. IEEE Computer Society, (2012)The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures., , , , and . ICS, page 351-360. ACM, (1989)Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture., , , , and . ICS, page 272-281. ACM, (1992)Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis., , , , , and . ASIAN, volume 1345 of Lecture Notes in Computer Science, page 268-282. Springer, (1997)SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture., , , and . ISCA, page 78-85. ACM, (1989)A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines., , , , and . ISCA, page 280-289. IEEE Computer Society, (1986)A Web-Based Education Tool for Collaborative Learning of Assembly Programming., and . ICWI, page 703-710. IADIS, (2003)Simulating realistic force and shape of virtual cloth with adaptive meshes and its parallel implementation in OpenMP., , , , , and . Parallel and Distributed Computing and Networks, page 386-391. IASTED/ACTA Press, (2004)