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High performance collision cross section calculation - HPCCS.

, , , , and . Journal of Computational Chemistry, 39 (21): 1675-1681 (2018)

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Computer security by hardware-intrinsic authentication., , , and . CODES+ISSS, page 143-152. IEEE, (2015)Code Compression Based on Operand Factorization., , , and . MICRO, page 194-201. ACM/IEEE Computer Society, (1998)Improving the Statistical Variability of Delay-based Physical Unclonable Functions., , and . SBCCI, page 41:1-41:7. ACM, (2015)CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence., , , and . Microprocessors and Microsystems - Embedded Hardware Design, (2018)The Case for Phase-Based Transactional Memory., , and . IEEE Trans. Parallel Distrib. Syst., 30 (2): 459-472 (2019)The ArchC Architecture Description Language and Tools., , , , , and . International Journal of Parallel Programming, 33 (5): 453-484 (2005)Computer security by hardware-intrinsic authentication., , , and . CODES+ISSS, page 143-152. IEEE, (2015)Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor., , and . J. UCS, 14 (21): 3465-3480 (2008)Challenges in code generation for embedded processors., , , , , , , and . Code Generation for Embedded Processors, page 48-64. Kluwer, (1994)Trace Execution Automata in Dynamic Binary Translation., , , and . ISCA Workshops, volume 6161 of Lecture Notes in Computer Science, page 99-116. Springer, (2010)