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CNTFET Modeling and Reconfigurable Logic-Circuit Design., , , , , , , , , and 2 other author(s). IEEE Trans. on Circuits and Systems, 54-I (11): 2365-2379 (2007)Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices., , , , , , , , , and 2 other author(s). IEEE Trans. on Circuits and Systems, 58-I (9): 2172-2181 (2011)Substrate-coupling effect in BiCMOS technology for millimeter wave applications., , , , , and . NEWCAS, page 1-4. IEEE, (2015)Modeling of Strained CMOS on Disposable SiGe Dots: Strain Impacts on Devices' Electrical Characteristics, , and . IEEE Transactions on Electron Devices, 54 (9): 2321-2326 (2007)A class-J power amplifier for 5G applications in 28nm CMOS FD-SOI technology., , and . SBCCI, page 110-113. ACM, (2017)Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation., , , , , and . ESSDERC, page 305-308. IEEE, (2014)Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance., , , , , , , , , and 1 other author(s). BCICTS, page 1-7. IEEE, (2021)Representation of the SiGe HBT's thermal impedance by linear and recursive networks., , , and . Microelectronics Reliability, 44 (6): 945-950 (2004)From nanoscale technology scenarios to compact device models for ambipolar devices., , and . ICECS, page 57-61. IEEE, (2010)Characterization and modeling of low-frequency noise in CVD-grown graphene FETs., , , , , , and . ESSDERC, page 176-179. IEEE, (2015)