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Disambiguation of "Lee, Sheayun"

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Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.

, , , , and . SCOPES, volume 2826 of Lecture Notes in Computer Science, page 33-48. Springer, (2003)

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Moosung Lee University of Stuttgart

Dongwon Lee University of Stuttgart

Junghwa Lee University of Stuttgart

Ph. D. Benjamin Lee University of Stuttgart

Yoonhee Lee University of Stuttgart

 

Other publications of authors with the same name

Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation., , , , and . SCOPES, volume 2826 of Lecture Notes in Computer Science, page 33-48. Springer, (2003)HIL: A Framework for Compositional FTL Development and Provably-Correct Crash Recovery., , , , , , , , , and . ACM Trans. Storage, 14 (4): 36:1-36:29 (2018)A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors., , , and . WCET, MDH-MRTC-116/2003-1-SE, page 91-94. Department of Computer Science and Engineering, Mälardalen University, Box 883, 721 23 Västerås, Sweden, (2003)Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study., , , , , , , , , and 4 other author(s). CODES+ISSS, page 235-240. ACM, (2006)Selective code transformation for dual instruction set processors., , , and . ACM Trans. Embedded Comput. Syst., 6 (2): 10 (2007)Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems., , , , and . LCTES, volume 1474 of Lecture Notes in Computer Science, page 51-64. Springer, (1998)P-BMS: A Bad Block Management Scheme in Parallelized Flash Memory Storage Devices., , , , and . ACM Trans. Embedded Comput. Syst., 16 (5s): 140:1-140:19 (2017)Cache-Conscious Limited Preemptive Scheduling., , , , and . Real-Time Systems, 17 (2-3): 257-282 (1999)A design framework for real-time embedded systems with code size and energy constraints., , , , and . ACM Trans. Embedded Comput. Syst., 7 (2): 18:1-18:27 (2008)A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor., , , and . SCOPES, volume 3199 of Lecture Notes in Computer Science, page 244-258. Springer, (2004)