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Dynamic Software Updating Using a Relaxed Consistency Model.

, , , , and . IEEE Trans. Software Eng., 37 (5): 679-694 (2011)

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: Data Prefetching In Shared Memory Multiprocessors., , and . ICPP, page 28-31. Pennsylvania State University Press, (1987)Performance Study of a Concurrent Multithreaded Processor., , , and . HPCA, page 24-35. IEEE Computer Society, (1998)Decoupled Value Prediction on Trace Processors., , and . HPCA, page 231-240. IEEE Computer Society, (2000)A fault tolerant interconnection network using error correcting codes., , and . ICPP, page 123-125. IEEE Computer Society, (1982)Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study., and . IEEE Trans. Parallel Distrib. Syst., 11 (4): 375-394 (2000)Editorial.. IEEE Trans. Parallel Distrib. Syst., 13 (1): 4 (2002)On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors., and . IEEE PACT, page 145-156. IEEE Computer Society, (2000)Distributing Hot-Spot Addressing in Large-Scale Multiprocessors., , and . IEEE Trans. Computers, 36 (4): 388-395 (1987)Interprocedural Induction Variable Analysis., and . ISPAN, page 245-250. IEEE Computer Society, (2002)A General Persistent Code Caching Framework for Dynamic Binary Translation (DBT)., , , and . USENIX Annual Technical Conference, page 591-603. USENIX Association, (2016)