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EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA.

H. Shibamura, M. Fukuyama, D. Uchida, S. Ikeda, M. Kuga, and T. Sueyoshi. FPT, page 209-216. IEEE, (2004)

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Other publications of authors with the same name

KITE microprocessor and CAE for computer science.T. Sueyoshi, M. Kuga, and H. Shibamura. Systems and Computers in Japan, 33 (8): 64-74 (2002)Performance prediction of large-scale parallell system and application using macro-level simulation.R. Susukita, H. Ando, M. Aoyagi, H. Honda, Y. Inadomi, K. Inoue, S. Ishizuki, Y. Kimura, H. Komatsu, M. Kurokawa and 4 other author(s). SC, page 20. IEEE/ACM, (2008)NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers.H. Miwa, R. Susukita, H. Shibamura, T. Hirao, J. Maki, M. Yoshida, T. Kando, Y. Ajima, I. Miyoshi, T. Shimizu and 6 other author(s). IEICE Transactions, 94-D (12): 2298-2308 (2011)Memory Efficient One-Sided Communucation Library ÄCP" in Globary Memory on Raspberry Pi 2.Y. Morie, H. Honda, T. Nanri, T. Kobayashi, H. Shibamura, R. Susukita, and Y. Ajima. ICDCS, page 761-762. IEEE Computer Society, (2016)Active Packet Pacing as a Congestion Avoidance Technique in Interconnection Network.H. Shibamura. PARCO, volume 27 of Advances in Parallel Computing, page 257-264. IOS Press, (2015)EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA.H. Shibamura, M. Fukuyama, D. Uchida, S. Ikeda, M. Kuga, and T. Sueyoshi. FPT, page 209-216. IEEE, (2004)Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.Y. Yang, H. Amano, H. Shibamura, and T. Sueyoshi. SPDP, page 591-595. IEEE Computer Society, (1993)NSIM-ACE: An Interconnection Network Simulator for Evaluating Remote Direct Memory Access.R. Susukita, Y. Morie, T. Nanri, and H. Shibamura. SIMULTECH, page 254-261. SciTePress, (2016)Recursive Diagonal Torus (RDT): An Interconnection Network for the Massively Parallel Computers.Y. Yang, H. Amano, H. Shibamura, and T. Sueyoshi. Systems and Computers in Japan, 27 (9): 43-54 (1996)

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Disambiguation of "Shibamura, Hidetomo"

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EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA.

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Disambiguation of "Shibamura, Hidetomo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA.

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EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA.