Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Analyzing Memory Access on CPU-GPGPU Shared LLC Architecture.

J. Ma, L. Yu, T. Chen, and M. Wu. ISPDC, page 90-99. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hanbing Ma University of Stuttgart

Yuliang Ma University of Stuttgart

Marcel Maier University of Stuttgart

Improving navigation resilience by using B-splines in the sensor fusion of multiple inertial measurement unitsM. Maier, T. Hobiger, and T. Topp. (May 2024)

Prof. Dr.-Ing. Thomas Maier Universität Stuttgart

Daniel Marino

Other publications of authors with the same name

Access Pattern Based Re-reference Interval Table for Last Level Cache.B. Yu, Y. Hu, J. Ma, and T. Chen. PDCAT, page 251-256. IEEE Computer Society, (2011)A Performance Model for Run-Time Reconfigurable Hardware Accelerator.G. Wang, D. Chen, J. Chen, J. Ma, and T. Chen. APPT, volume 5737 of Lecture Notes in Computer Science, page 54-66. Springer, (2009)Function Units Sharing between Neighbor Cores in CMP.T. Chen, J. Ma, H. Yuan, J. Liu, and G. Jiang. ICA3PP (1), volume 6081 of Lecture Notes in Computer Science, page 136-148. Springer, (2010)Improve LLC Bypassing Performance by Memory Controller Improvements in Heterogeneous Multicore System.J. Ma, J. Meng, T. Chen, Q. Shi, M. Wu, and L. Liu. PDCAT, page 82-89. IEEE Computer Society, (2014)Global Priority Table for Last-Level Caches.B. Yu, J. Ma, T. Chen, and M. Wu. DASC, page 279-285. IEEE Computer Society, (2011)Global register alias table: Boosting sequential program on multi-core.J. Ma, C. Wang, B. Yu, and T. Chen. Future Generation Comp. Syst., 28 (6): 957-964 (2012)MCMG simulator: A unified simulation framework for CPU and graphic GPU.J. Ma, L. Yu, J. Ye, and T. Chen. J. Comput. Syst. Sci., 81 (1): 57-71 (2015)Making GPU Warp Scheduler and Memory Scheduler Synchronization-Aware.J. Ma, T. Chen, and M. Wu. CloudCom-Asia, volume 9106 of Lecture Notes in Computer Science, page 153-164. Springer, (2015)Improve GPGPU Latency Hiding with a Hybrid Recovery Stack and a Window Based Warp Scheduling Policy.T. Chen, X. Tang, L. Yu, J. Ma, and M. Wu. HPCC-ICESS, page 1288-1293. IEEE Computer Society, (2012)Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System.S. Li, J. Meng, L. Yu, J. Ma, T. Chen, and M. Wu. HPCC/CSS/ICESS, page 266-271. IEEE, (2015)

PUMA

Disambiguation of "Ma, Jianliang"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Analyzing Memory Access on CPU-GPGPU Shared LLC Architecture.

Please choose a person to relate this publication to

Hanbing Ma University of Stuttgart

Yuliang Ma University of Stuttgart

Marcel Maier University of Stuttgart

Prof. Dr.-Ing. Thomas Maier Universität Stuttgart

Daniel Marino

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Ma, Jianliang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Analyzing Memory Access on CPU-GPGPU Shared LLC Architecture.

Please choose a person to relate this publication to

Hanbing Ma University of Stuttgart

Yuliang Ma University of Stuttgart

Marcel Maier University of Stuttgart

Prof. Dr.-Ing. Thomas Maier Universität Stuttgart

Daniel Marino

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Analyzing Memory Access on CPU-GPGPU Shared LLC Architecture.