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A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture., , , , , and . IPDPS, IEEE Computer Society, (2005)An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC., , , , , , , , , and 2 other author(s). IEEE Design & Test of Computers, 25 (5): 442-451 (2008)Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array., , , , , , , , , and . DATE, page 1444-1449. ACM, (2008)Design and implementation of a reconfigurable heterogeneous multiprocessor SoC., , , , , , , and . CICC, page 93-96. IEEE, (2006)A dynamically adaptive DSP for heterogeneous reconfigurable platforms., , , , , , , , and . DATE, page 9-14. EDA Consortium, San Jose, CA, USA, (2007)A stream register file unit for reconfigurable processors., , , , , , and . ISCAS, IEEE, (2006)Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor., , , , , , , , , and 6 other author(s). DATE, page 1352-1357. ACM, (2008)