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From model to FPGA: Software-hardware co-design for efficient neural network acceleration.

K. Guo, L. Sui, J. Qiu, S. Yao, S. Han, Y. Wang, and H. Yang. Hot Chips Symposium, page 1-27. IEEE, (2016)

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Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware.K. Guo, L. Sui, J. Qiu, S. Yao, S. Han, Y. Wang, and H. Yang. ISVLSI, page 24-29. IEEE Computer Society, (2016)A High-Performance CNN Processor Based on FPGA for MobileNets.D. Wu, Y. Zhang, X. Jia, L. Tian, T. Li, L. Sui, D. Xie, and Y. Shan. FPL, page 136-143. IEEE, (2019)An In-depth Comparison of Compilers for Deep Neural Networks on Hardware.Y. Xing, J. Weng, Y. Wang, L. Sui, Y. Shan, and Y. Wang. ICESS, page 1-8. IEEE, (2019)Real-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning Networks.S. Fang, L. Tian, J. Wang, S. Liang, D. Xie, Z. Chen, L. Sui, Q. Yu, X. Sun, Y. Shan and 1 other author(s). FPT, page 389-392. IEEE, (2018)From model to FPGA: Software-hardware co-design for efficient neural network acceleration.K. Guo, L. Sui, J. Qiu, S. Yao, S. Han, Y. Wang, and H. Yang. Hot Chips Symposium, page 1-27. IEEE, (2016)Real-Time Pedestrian Detection and Tracking on Customized Hardware.J. Wang, K. Yan, K. Guo, J. Yu, L. Sui, S. Yao, S. Han, and Y. Wang. ESTIMedia, page 1. ACM, (2016)Time-varying channel estimation based on dynamic compressive sensing for OFDM systems.Y. Han, P. Zhao, L. Sui, and Z. Fan. BMSB, page 1-5. IEEE, (2014)DNNVM: End-to-End Compiler Leveraging Operation Fusion on FPGA-based CNN Accelerators.Y. Xing, S. Liang, L. Sui, Z. Zhang, J. Qiu, X. Jia, X. Liu, Y. Wang, Y. Shan, and Y. Wang. FPGA, page 187-188. ACM, (2019)DNNVM : End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-based CNN Accelerators.Y. Xing, S. Liang, L. Sui, X. Jia, J. Qiu, X. Liu, Y. Wang, Y. Wang, and Y. Shan. CoRR, (2019)

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Disambiguation of "Sui, Lingzhi"

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From model to FPGA: Software-hardware co-design for efficient neural network acceleration.

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Disambiguation of "Sui, Lingzhi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML From model to FPGA: Software-hardware co-design for efficient neural network acceleration.

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From model to FPGA: Software-hardware co-design for efficient neural network acceleration.