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Disambiguation of "Rubio, Antonio"

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Noise Generation and Coupling Mechanisms in Deep-Submicron ICs.

, , , and . IEEE Design & Test of Computers, 19 (5): 27-35 (2002)

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Antonio Raiolo University of Stuttgart

Giuliano Antonio Giacoppo University of Stuttgart

Jesus Antonio Martinez Zarate University of Stuttgart

Dr. phil. Rafael Antonio Lainez Reyes University of Stuttgart

 

Other publications of authors with the same name

An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits., , , and . Microelectronics Journal, 36 (1): 77-84 (2005)An Approach to the Development of a IDDQ Testable Cell Library., , , , and . DFT, page 46-54. IEEE Computer Society, (1994)Using Temperature as Observable of the Frequency Response of RF CMOS Amplifiers., , , , , , , , , and 1 other author(s). European Test Symposium, page 47-52. IEEE Computer Society, (2008)Selective Clock-Gating for Low-Power Synchronous Counters., , and . J. Low Power Electronics, 1 (3): 217-225 (2005)Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells., , , , and . Integration, 45 (3): 246-252 (2012)An approach to dynamic power consumption current testing of CMOS ICs., , , and . VTS, page 95-100. IEEE Computer Society, (1995)Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 13 (3): 359-369 (1994)Current testability analysis of feedback bridging faults in CMOS circuits., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 14 (10): 1299-1305 (1995)Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies., , and . IEEE Trans. Emerging Topics Comput., 6 (2): 207-218 (2018)New redundant logic design concept for high noise and low voltage scenarios., , , , , and . Microelectronics Journal, 42 (12): 1359-1369 (2011)