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mm USR Link in 16nm FinFET.

A. Tajalli, M. Bastani, D. Carnelli, C. Cao, J. Fox, K. Gharibdoust, D. Gorret, A. Gupta, C. Hall, A. Hassanin, K. Hofstra, B. Holden, A. Hormati, J. Keay, Y. Mogentale, G. Paul, V. Perrin, J. Phillips, S. Raparthy, A. Shokrollahi, D. Stauffer, R. Simpson, A. Stewart, G. Surace, O. Amiri, A. Truffa, A. Tschank, R. Ulrich, C. Walter, and A. Singh. VLSI Circuits, page 92-. IEEE, (2019)

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Prof. Dr. Armin Hermann University of Stuttgart

Armin Kammer University of Stuttgart

Dr. -Ing. Armin Lechler University of Stuttgart

Dr. Armin Weiß University of Stuttgart

Prof. Dr. Armin Schmidt University of Stuttgart

Other publications of authors with the same name

A duty cycle control circuit for high speed applications.A. Tajalli, S. Mehrmanesh, and S. Atarodi. ISCAS (1), page 781-784. IEEE, (2004)A Power Optimized Base-Band Circuitry for the Low-IF Receivers.R. Zanbaghi, S. Atarodi, and A. Tajalli. ISCAS, page 1693-1696. IEEE, (2007)Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL.A. Tajalli, and Y. Leblebici. IEEE Trans. on Circuits and Systems, 59-II (12): 903-907 (2012)Design trade-offs in ultra-low-power CMOS and STSCL digital systems.A. Tajalli, and Y. Leblebici. ECCTD, page 544-547. IEEE, (2011)A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS.K. Gharibdoust, A. Tajalli, and Y. Leblebici. VLSIC, page 180-. IEEE, (2015)A low-power, multichannel gated oscillator-based CDR for short-haul applications.A. Tajalli, P. Muller, S. Atarodi, and Y. Leblebici. ISLPED, page 107-110. ACM, (2005)A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET.A. Tajalli, M. Parizi, D. Carnelli, C. Cao, K. Gharibdoust, D. Gorret, A. Gupta, C. Hall, A. Hassanin, K. Hofstra and 18 other author(s). J. Solid-State Circuits, 55 (4): 1108-1123 (2020)Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.A. Tajalli, M. Alioto, E. Brauer, and Y. Leblebici. PATMOS, volume 5349 of Lecture Notes in Computer Science, page 21-30. Springer, (2008)A compact, low power, fully integrated clock frequency doubler.A. Tajalli, A. Khodaverdi, and S. Atarodi. ICECS, page 563-566. IEEE, (2003)Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators.M. Shoaran, A. Tajalli, M. Alioto, and Y. Leblebici. ISCAS, page 157-160. IEEE, (2015)

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A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET.

Please choose a person to relate this publication to

Prof. Dr. Armin Hermann University of Stuttgart

Armin Kammer University of Stuttgart

Dr. -Ing. Armin Lechler University of Stuttgart

Dr. Armin Weiß University of Stuttgart

Prof. Dr. Armin Schmidt University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Tajalli, Armin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET.

Please choose a person to relate this publication to

Prof. Dr. Armin Hermann University of Stuttgart

Armin Kammer University of Stuttgart

Dr. -Ing. Armin Lechler University of Stuttgart

Dr. Armin Weiß University of Stuttgart

Prof. Dr. Armin Schmidt University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET.