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A Case for Clumsy Packet Processors., and . MICRO, page 147-156. IEEE Computer Society, (2004)Low Power Correlating Caches for Network Processors., and . J. Low Power Electronics, 1 (2): 108-118 (2005)Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming., , and . CODES+ISSS, page 267-276. ACM, (2010)A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms., , , , , , and . DAC, page 549-554. ACM, (2010)Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling., , , , , , , , , and 15 other author(s). ICICDT, page 145-148. IEEE, (2018)Smart bit-width allocation for low power optimization in a systemc based ASIC design environment., , , and . DATE, page 618-623. European Design and Automation Association, Leuven, Belgium, (2006)Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files., , , and . DSN, page 770-779. IEEE Computer Society, (2005)Variable latency caches for nanoscale processor., , , , and . SC, page 20. ACM Press, (2007)The user in experimental computer systems research., , , , , , and . Experimental Computer Science, page 10. ACM, (2007)User- and process-driven dynamic voltage and frequency scaling., , , , and . ISPASS, page 11-22. IEEE Computer Society, (2009)