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Optimizing Program Locality Through CMEs and GAs., , , and . IEEE PACT, page 68-78. IEEE Computer Society, (2003)Improved spill code generation for software pipelined loops., , , and . PLDI, page 134-144. ACM, (2000)Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , and . International Journal of Parallel Programming, 32 (6): 447-474 (2004)Register Constrained Modulo Scheduling., , , and . IEEE Trans. Parallel Distrib. Syst., 15 (5): 417-430 (2004)Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units., , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 88-97. Springer, (2004)A comparative study of modulo scheduling techniques., , and . ICS, page 97-106. ACM, (2002)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Heuristics for Register-Constrained Software Pipelining., , and . MICRO, page 250-261. ACM/IEEE Computer Society, (1996)Distributed Modulo Scheduling., , and . HPCA, page 130-134. IEEE Computer Society, (1999)Merge Logic for Clustered Multithreaded VLIW Processors., , and . DSD, page 353-360. IEEE Computer Society, (2007)