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Disambiguation of "Pattanaik, Manisha"

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Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application.

, , and . DSD, page 404-407. IEEE Computer Society, (2010)

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Other publications of authors with the same name

Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits., and . J. Low Power Electronics, 10 (1): 45-52 (2014)High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell., , and . Wireless Personal Communications, 78 (1): 57-68 (2014)A novel dual multiplier floating point multiply accumulate architecture., and . VDAT, page 1-2. IEEE, (2015)Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology., , , , and . Circuits and Systems, 2 (4): 326-329 (2011)A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate., , and . ISED, page 151-153. IEEE, (2012)A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique., , , , and . ISED, page 118-123. IEEE Computer Society, (2011)Operation-aware assist circuit design for improved write performance of FinFET based SRAM., , , and . VDAT, page 1-6. IEEE, (2014)Techniques for Low Leakage nanoscale VLSI Circuits: a Comparative Study., and . Journal of Circuits, Systems, and Computers, (2014)PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits., , and . Microelectronics Reliability, 54 (1): 90-99 (2014)A New Adaptive Thresholding in SVD for Efficient Image De-noising., , and . SocProS (2), volume 131 of Advances in Intelligent and Soft Computing, page 659-670. Springer, (2011)