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Two-path operational amplifier using FDSOI CMOS with first fast low-gain and second slow high-gain path for fast regulated voltage buffers with low offset error, , , and . Analog Workshop, (2025)Charge Based Mixed-Signal Multiply-Accumulate Circuit for Energy Efficient In-Memory Computing, , , , , , and . Proceedings of the 2021 Kleinheubach Conference, Piscataway, IEEE, (2021)Characterization of a Femtojoule Voltage-to-Time Converter with Rectified Linear Unit Characteristic for Analog Neural Network Inference Accelerators, , , , and . 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), page 253-257. IEEE, (2024)Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators, , , , and . IEEE transactions on circuits and systems. 1, Regular papers, 70 (9): 3509-3521 (2023)140 GHz Transmitter Chip for Pseudo Random Noise Radar in 22 nm FD-SOI CMOS Technology, , and . page 22. (2021)Characterization of an Analog MAC Cell with Multi-Bit Resolution for AI Inference Accelerators, , , , and . 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), page 243-247. IEEE, (2024)Characterization of a Femtojoule Voltage-to-Time Converter with Rectified Linear Unit Characteristic for Analog Neural Network Inference Accelerators, , , , and . IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), (2024)Glitch-freier, jitterarmer Amplituden- und Phasenschalter für digitale RF-Pulsmodulation, , , , , and . Analog Workshop, (2025)Analoge Berechnung von Künstlichen Neuronalen Netzen in 22 nm FD-SOI CMOS, , , , , and . Analog Workshop, (2025)Characterization of an Analog MAC Cell with Multi-Bit Resolution for AI Inference Accelerators, , , , and . IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), (2024)