PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Yao, Hailong"

Author of the publication

copydeleteadd this publication to your clipboard
CMP-aware Maze Routing Algorithm for Yield Enhancement.

, , and . ISVLSI, page 239-244. IEEE Computer Society, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yao Wang University of Stuttgart

 

Other publications of authors with the same name

LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits., , and . ASP-DAC, page 157-162. IEEE, (2012)Layout Decomposition Approaches for Double Patterning Lithography., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (6): 939-952 (2010)Congestion-driven W-shape multilevel full-chip routing framework., , and . ISCAS, IEEE, (2006)More Effective Randomly-Designed Microfluidics., , and . ISVLSI, page 660-665. IEEE Computer Society, (2018)LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips., , , , and . ACM Great Lakes Symposium on VLSI, page 447-450. ACM, (2017)Sequence-pair-based placement and routing for flow-based microfluidic biochips., , , , and . ASP-DAC, page 587-592. IEEE, (2016)Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization., , , , , and . ACM Great Lakes Symposium on VLSI, page 199-204. ACM, (2011)An Approach to Information Fusion and Group Deecision Making Based on Choquet Integral Operators for Interval-Valued Intuitionistic Fuzzy Data., and . ICMLC, page 109-114. IEEE, (2018)Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture., , , , , , and . DAC, page 80:1-80:6. ACM, (2017)CMP-aware Maze Routing Algorithm for Yield Enhancement., , and . ISVLSI, page 239-244. IEEE Computer Society, (2007)