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Serial-Link Bus: A Low-Power On-Chip Bus Architecture., , , , and . IEEE Trans. on Circuits and Systems, 56-I (9): 2020-2032 (2009)A novel digital loop filter architecture for bang-bang ADPLL., , , , , , , and . SoCC, page 45-50. IEEE, (2012)A novel power gated digitally controlled oscillator., , and . ICEAC, page 1-4. IEEE, (2011)Low-power on-chip bus architecture using dynamic relative delays., and . SoCC, page 233-236. IEEE, (2004)Effect of relative delay on the dissipated energy in coupled interconnects., and . ISCAS (2), page 525-528. IEEE, (2004)Formal derivation of optimal active shielding for low-power on-chip buses., and . ICCAD, page 800-807. IEEE Computer Society / ACM, (2004)High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network., , and . IntelliSys (1), volume 868 of Advances in Intelligent Systems and Computing, page 655-663. Springer, (2018)SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus., , , and . IEEE Trans. on Circuits and Systems, 56-I (2): 384-394 (2009)Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques., , , , and . IEEE Trans. on Circuits and Systems, 53-I (9): 1928-1933 (2006)Reducing the Data Switching Activity on Serial Link Buses., , , and . ISQED, page 425-432. IEEE Computer Society, (2006)