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Hardware Design Automation of Convolutional Neural Networks., , , , , and . ISVLSI, page 224-229. IEEE Computer Society, (2016)Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project., , , , , and . DATE, page 410-415. IEEE, (2017)Tiramisu: A Polyhedral Compiler for Expressing Fast and Portable Code., , , , , , , , and . CGO, page 193-205. IEEE, (2019)OXiGen: A Tool for Automatic Acceleration of C Functions Into Dataflow FPGA-Based Kernels., , , and . IPDPS Workshops, page 91-98. IEEE Computer Society, (2018)Speeding Up Resting State Networks Recognition via a Hardware Accelerator., , , , , , and . BHI, page 1-4. IEEE, (2019)A Scalable FPGA Design for Cloud N-Body Simulation., , , , and . ASAP, page 1-8. IEEE Computer Society, (2018)A Unified Backend for Targeting FPGAs from DSLs., , , and . ASAP, page 1-8. IEEE Computer Society, (2018)Five-point algorithm: An efficient cloud-based FPGA implementation., , , and . ASAP, page 1-8. IEEE Computer Society, (2018)Tiramisu: A Polyhedral Compiler for Expressing Fast and Portable Code., , , , , , , , and . CoRR, (2018)A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project., , , , , , , , and . ISVLSI, page 368-373. IEEE Computer Society, (2017)