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Sub-100 nm CMOS circuit performance with high-K gate dielectrics.

N. Mohapatra, A. Dutta, G. Sridhar, M. Desai, and V. Rao. Microelectronics Reliability, 41 (7): 1045-1048 (2001)

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V. Vaikuntanathan

V. Zaverkin

Samaneh Vahid Dastjerdi University of Stuttgart

Primary drainage experiments and fractal dimensionsN. Karadimitriou, D. Lee, S. Vahid Dastjerdi, and H. Steeb. Dataset, (2024)

Michael P. Voigt Universität Stuttgart

Wolfgang Vogel

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Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness.Y. Kobayashi, K. Kakushima, P. Ahmet, V. Rao, K. Tsutsui, and H. Iwai. Microelectronics Reliability, 50 (3): 332-337 (2010)Physics and Technology: Towards Low-Power DSM Design.D. Mukhopadhyay, P. Basu, and V. Rao. VLSI Design, page 16-17. IEEE Computer Society, (2005)Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.D. Kumar, N. Mohapatra, M. Patil, and V. Rao. VLSI Design, page 128-. IEEE Computer Society, (2003)erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering.G. Shrivastav, S. Mahapatra, V. Rao, J. Vasi, K. Anil, C. Fink, W. Hansch, and I. Eisele. VLSI Design, page 475-478. IEEE Computer Society, (2001)Circuit Optimization at 22nm Technology Node.A. Sachid, P. Paliwal, S. Joshi, M. Shojaei, D. Sharma, and V. Rao. VLSI Design, page 322-327. IEEE Computer Society, (2012)The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance.K. Narasimhulu, S. Narendra, and V. Rao. VLSI Design, page 545-550. IEEE Computer Society, (2004)Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.N. Mohapatra, M. Desai, and V. Rao. VLSI Design, page 99-104. IEEE Computer Society, (2003)Current Excitation Method for DeltaR Measurement in Piezo-Resistive Sensors With a 0.3-ppm Resolution.N. Gilda, S. Nag, S. Patil, M. Baghini, D. Sharma, and V. Rao. IEEE Trans. Instrumentation and Measurement, 61 (3): 767-774 (2012)A novel architecture for improving slew rate in FinFET-based op-amps and OTAs.R. Thakker, M. Srivastava, K. Tailor, M. Baghini, D. Sharma, V. Rao, and M. Patil. Microelectronics Journal, 42 (5): 758-765 (2011)Low power, area efficient, and temperature-variation tolerant bidirectional current source for sensor applications.N. Gilda, H. Gopal, D. Sharma, V. Rao, and M. Baghini. Microelectronics Journal, (2016)

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Disambiguation of "Rao, V. Ramgopal"

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Sub-100 nm CMOS circuit performance with high-K gate dielectrics.

Please choose a person to relate this publication to

V. Vaikuntanathan

V. Zaverkin

Samaneh Vahid Dastjerdi University of Stuttgart

Michael P. Voigt Universität Stuttgart

Wolfgang Vogel

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Rao, V. Ramgopal"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Sub-100 nm CMOS circuit performance with high-K gate dielectrics.

Please choose a person to relate this publication to

V. Vaikuntanathan

V. Zaverkin

Samaneh Vahid Dastjerdi University of Stuttgart

Michael P. Voigt Universität Stuttgart

Wolfgang Vogel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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APA
Chicago
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Sub-100 nm CMOS circuit performance with high-K gate dielectrics.