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Disambiguation of "Baas, Bevan M."

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AsAP: An Asynchronous Array of Simple Processors.

, , , , , , , , , and . J. Solid-State Circuits, 43 (3): 695-705 (2008)

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M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

M. Christmann

 

Other publications of authors with the same name

A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System., and . IEEE Trans. Circuits Syst. Video Techn., 21 (7): 890-902 (2011)A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (6): 897-910 (2010)A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks., and . VLSI-SoC (Selected Papers), volume 418 of IFIP Advances in Information and Communication Technology, page 125-143. Springer, (2012)AsAP: An Asynchronous Array of Simple Processors., , , , , , , , , and . J. Solid-State Circuits, 43 (3): 695-705 (2008)Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" Integr. VLSI J. 58. (2017) 74-81., and . Integration, (2019)Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles., and . ICCD, page 174-179. IEEE, (2006)KiloCore: A 32 nm 1000-processor array., , , , , , , and . Hot Chips Symposium, page 1-23. IEEE, (2016)Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems., and . ISVLSI, page 378-383. IEEE Computer Society, (2006)A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform., , and . ACSCC, page 2067-2071. IEEE, (2011)A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors., and . IEEE Trans. VLSI Syst., 18 (5): 750-762 (2010)