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Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems., and . ICECS, page 919-922. IEEE, (2007)Towards satisfaction checking of power contracts in Uppaal., , and . FDL, page 1-8. IEEE, (2014)A methodology for scaling power dissipation values between different FPGAs., and . PATMOS, page 1-8. IEEE, (2014)New approach in gate-level glitch modelling., and . EURO-DAC, page 66-71. IEEE Computer Society Press, (1996)Modelling and Synthesis of Communication Using OSSS-Channels., , , and . MBMV, page 38-47. Fraunhofer Institut für Integrierte Schaltungen, (2006)Profilbasierte Energieabschätzung integrierter Schaltungen auf algorithmischer Ebene., , , and . MBMV, page 131-140. Institut für Angewandte Mikroelektronik und Datentechnik, Fakultät für Informatik und Elektrotechnik, Universität Rostock, (2013)Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits., and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 117-126. Springer, (2006)A New Parameterizable Power Macro-Model for Datapath Components., , , and . DATE, page 29-. IEEE Computer Society / ACM, (1999)Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids., and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 735-736. Springer, (2005)Eine Fallstudie zur dynamischen Rekonfiguration von Hardware: "Pain or Gain?"., , and . MBMV, page 243-252. Shaker, (2007)