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A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS., , and . SoCC, page 35-39. IEEE, (2015)A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS., , , , , and . J. Solid-State Circuits, 54 (3): 845-855 (2019)Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS., , , , and . SoCC, page 253-257. IEEE, (2017)A 1-pJ/bit 80-Gb/s $2^15-1$ PRBS Generator With a Modified Cherry-Hooper Output Driver., , and . J. Solid-State Circuits, 54 (7): 2059-2069 (2019)A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS., , , and . ISCAS, page 2385-2388. IEEE, (2015)A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends., , , and . VLSI-SoC, page 46-51. IEEE, (2019)A 50 Gb/s 190 mW Asymmetric 3-Tap FFE VCSEL Driver., , , and . J. Solid-State Circuits, 52 (9): 2422-2429 (2017)Survey of Photonic and Plasmonic Interconnect Technologies for Intra-Datacenter and High-Performance Computing Communications., , , , , , , , , and . IEEE Communications Surveys and Tutorials, 20 (4): 2758-2783 (2018)A 30 Gb/s High-Swing, Open-Collector Modulator Driver in 250 nm SiGe BiCMOS., , , , and . MWSCAS, page 5-8. IEEE, (2018)A Highly Adaptive and Energy-Efficient Optical Interconnect for On-Board Server Communications., , , , , and . ICCCN, page 1-8. IEEE, (2017)