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A LVDS Serial AER Link., , , , , , , and . ICECS, page 938-941. IEEE, (2006)The Stochastic I-Pot: A Circuit Block for Programming Bias Currents., , , , and . IEEE Trans. on Circuits and Systems, 54-II (9): 760-764 (2007)AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems., , , , , , , , , and 8 other author(s). NIPS, page 1217-1224. (2005)On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing., , , , , , , , and . IEEE Trans. Neural Networks, 19 (7): 1196-1219 (2008)High-speed image processing with AER-based components., , , , , , and . ISCAS, IEEE, (2006)A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems., , , and . IEEE Trans. on Circuits and Systems, 53-I (12): 2548-2566 (2006)Spike Events Processing for Vision Systems., , , , , , and . ISCAS, page 841-844. IEEE, (2007)Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques., , and . ISCAS (1), page 301-304. IEEE, (2004)On mismatch properties of MOS and resistors calibrated ladder structures., , , and . ISCAS (1), page 377-380. IEEE, (2004)LVDS interface for AER links with burst mode operation capability., , , and . ISCAS, page 644-647. IEEE, (2008)