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Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs., , , and . ISQED, page 595-601. IEEE Computer Society, (2007)An overview of a compiler for mapping MATLAB programs onto FPGAs.. ASP-DAC, page 477-482. ACM, (2003)Open Innovation at HP Labs., , and . IEEE Computer, 43 (11): 88-90 (2010)An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design., and . IEEE Trans. Computers, 54 (7): 886-896 (2005)A software pipelining algorithm in high-level synthesis for FPGA architectures., , , , and . ISQED, page 297-302. IEEE Computer Society, (2009)Adaptive computing: what can it do, where can it go?, , , , , , and . ASP-DAC, page 463. ACM, (2003)Power Optimization of Delay Constrained Circuits., , , , and . VLSI Design, 2001 (2): 125-138 (2001)Hybrid Digital Twins: A Primer on Combining Physics-Based and Data Analytics Approaches., , , , , and . IEEE Softw., 39 (2): 47-52 (2022)Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code., , , and . LCPC, volume 4339 of Lecture Notes in Computer Science, page 76-90. Springer, (2005)Automatic Generation of Stream Descriptors for Streaming Architectures., , , , and . ICPP, page 307-312. IEEE Computer Society, (2010)