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Disambiguation of "Sapatnekar, Sachin S."

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An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.

, , and . ISPD, page 68-73. ACM, (2002)

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S. Schumann

S. Seemann

S. Wartzack

Boettinger S

S. Toro

 

Other publications of authors with the same name

Physical Design for Three-Dimensional Circuits., and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic., , and . ICCD, page 276-281. (1998)Capturing the Effect of Crosstalk on Delay.. VLSI Design, page 364-369. IEEE Computer Society, (2000)Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs., and . VLSI Design, page 346-351. IEEE Computer Society, (1996)Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up., and . ASP-DAC, page 87-92. ACM Press, (2005)Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity., , and . IEEE Design & Test of Computers, 26 (5): 15-25 (2009)DAC Highlights., and . IEEE Design & Test of Computers, 24 (5): 502-504 (2007)Process and Reliability Sensors for Nanoscale CMOS., , , and . IEEE Design & Test of Computers, 29 (5): 8-17 (2012)CATALYST: planning layer directives for effective design closure., , , , , and . DATE, page 1873-1878. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Improving STT-MRAM density through multibit error correction., , , and . DATE, page 1-6. European Design and Automation Association, (2014)