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A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters., and . IEEE Trans. on Circuits and Systems, 55-I (6): 1546-1559 (2008)A Row-Parallel 8$\, \times\, $ 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation., , , , , , and . IEEE Trans. Circuits Syst. Video Techn., 22 (6): 915-929 (2012)Systolic-array 3D wave-digital beam filters., and . APCCAS, page 1055-1058. IEEE, (2010)Directional spectrum sensing using tunable multi-D space-time discrete filters., , , , , and . WOWMOM, page 1-6. IEEE Computer Society, (2012)Design of a millimeter-wave dish-antenna based 3-D IIR radar digital velocity filter., , and . nDS, page 1-6. IEEE, (2015)FPGA architectures for real-time 2D/3D FIR/IIR plane wave filters., , and . ISCAS (3), page 613-616. IEEE, (2004)Multiplierless Approximate 4-point DCT VLSI Architectures for Transform Block Coding., , , and . CoRR, (2014)Deep learning based doppler radar for micro UAS detection and classification., , , and . MILCOM, page 924-929. IEEE, (2016)Massively parallel systolic-array architectures for 2d IIR polyphase space-time plane-wave beam digital filters., , and . I. J. Circuit Theory and Applications, 40 (5): 455-475 (2012)A Discrete Tchebichef Transform Approximation for Image and Video Coding., , , , and . CoRR, (2015)