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Disambiguation of "Nakano, Hirofumi"

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Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP.

, , , , and . ISHPC, volume 2327 of Lecture Notes in Computer Science, page 479-489. Springer, (2002)

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Other publications of authors with the same name

Bolt Tightening Using Impact Wrench Based on Neural Networks., , , and . JRM, 12 (6): 706-711 (2000)A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture., , , , , , , and . Trans. HiPEAC, (2011)Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API., , , , , , , and . ISPA, page 600-607. IEEE Computer Society, (2008)Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation., , , , , , and . SoCC, page 519-524. IEEE, (2010)A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement., , , , , , , , , and 4 other author(s). ISQED, page 16-23. IEEE, (2014)Multigrain Automatic Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler., , , , , , , , , and . PARELEC, page 105-111. IEEE Computer Society, (2002)Performance Evaluation of Compiler Controlled Power Saving Scheme., , , , , , , and . ISHPC, volume 4759 of Lecture Notes in Computer Science, page 480-493. Springer, (2005)Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP., , , , and . International Journal of Parallel Programming, 31 (3): 211-223 (2003)A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , and . SoCC, page 143-147. IEEE, (2012)Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP., , , , and . ISHPC, volume 2327 of Lecture Notes in Computer Science, page 479-489. Springer, (2002)