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Disambiguation of "Jr., Earl E. Swartzlander"

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A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.

, , and . VLSI Signal Processing, 31 (2): 77-89 (2002)

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E. Zafeiriou

E. Garrelts

P. E. Bl\"ochl

Andr{\'{e}} Buchau

Umm-E Habiba University of Stuttgart

 

Other publications of authors with the same name

Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS., , , , and . ASAP, page 335-343. IEEE Computer Society, (2002)Merged Arithmetic for Computing Wavelet Transforms., and . Great Lakes Symposium on VLSI, page 196-201. IEEE Computer Society, (1998)Parallel Counters.. IEEE Trans. Computers, 22 (11): 1021-1024 (1973)Editorial.. VLSI Signal Processing, 1 (3): 167 (1989)VLSI Concurrent Error Correcting Adders and Multipliers., and . DFT, page 287-294. IEEE Computer Society, (1993)The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-22. Springer, (2007)The hazard-free superscalar pipeline fast fourier transform algorithm and architecture., , and . VLSI-SoC, page 194-199. IEEE, (2007)Estimating the power consumption of CMOS adders., and . IEEE Symposium on Computer Arithmetic, page 210-216. IEEE Computer Society/, (1993)Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead., , and . IEEE Symposium on Computer Arithmetic, page 115-. IEEE Computer Society, (1995)Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor., and . IEEE Symposium on Computer Arithmetic, page 222-229. IEEE Computer Society, (1995)