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Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation.

N. Oda, H. Imura, N. Kawahara, M. Tagami, H. Kunishima, S. Sone, S. Ohnishi, K. Yamada, Y. Kakuhara, M. Sekine, Y. Hayashi, and K. Ueno. IEICE Transactions, 90-C (4): 848-855 (2007)

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Variationally determined electronic states for the theoretical analysis of intramolecular interaction. II. Qualitative nature of the P‒O bond in phosphine oxides.K. Yamada, and N. Koga. Journal of Computational Chemistry, 34 (2): 149-161 (2013)Relationships between market impact characteristics and order book properties.K. Yamada, and T. Mizuno. BigData, page 3156-3161. IEEE Computer Society, (2017)Detecting two types of seasonal words using simple autocorrelation analysis.K. Yamada. BigData, page 3162-3167. IEEE Computer Society, (2017)Ambiguity-driven Interaction in Robot-to-Human Teaching.K. Yamada, and J. Miura. HAI, page 257-260. ACM, (2016)Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications).K. Yamada, and N. Oda. IEICE Transactions, 91-C (4): 562-570 (2008)Application-level and user-level QoS assessment of audio-video transmission with EDCA of IEEE 802.11e.T. Suzuki, K. Yamada, M. Kato, and S. Tasaka. PIMRC, page 2727-2733. IEEE, (2005)A minimal implementation of the AMBER-GAUSSIAN interface for ab initio QM/MM-MD simulation.T. Okamoto, K. Yamada, Y. Koyano, T. Asada, N. Koga, and M. Nagaoka. Journal of Computational Chemistry, 32 (5): 932-942 (2011)Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns.K. Yamada, T. Syo, H. Yoshimura, M. Ito, T. Kunikiyo, T. Kanamoto, and S. Kumashiro. IEICE Transactions, 93-C (8): 1349-1358 (2010)Accurate Modeling Method for Cu Interconnect.K. Yamada, H. Kitahara, Y. Asai, H. Sakamoto, N. Okada, M. Yasuda, N. Oda, M. Sakurai, M. Hiroi, T. Takewaki and 4 other author(s). IEICE Transactions, 91-C (6): 968-977 (2008)Empirical analysis of collective human behavior for extraordinary events in blogosphereY. Sano, K. Yamada, H. Watanabe, H. Takayasu, and M. Takayasu. CoRR, (2011)

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Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation.

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Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation.