Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.

D. Bol, M. Schramme, L. Moreau, T. Haine, P. Xu, C. Frenkel, R. Dekimpe, F. Stas, and D. Flandre. ISSCC, page 322-324. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. Marie Davidova University of Stuttgart

Steffen Boley University of Stuttgart

Diego Bolanos Papenfort University of Stuttgart

Dr. Angela Boley University of Stuttgart

Steffen Bold University of Stuttgart

Other publications of authors with the same name

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.S. Clerc, M. Saligane, F. Abouzeid, M. Cochet, J. Daveau, C. Bottoni, D. Bol, J. Vos, D. Zamora, B. Coeffic and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)Impact of Technology Scaling on Digital Subthreshold Circuits.D. Bol, R. Ambroise, D. Flandre, and J. Legat. ISVLSI, page 179-184. IEEE Computer Society, (2008)A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range.D. Bol, G. de Streel, F. Botman, A. Lusala, and N. Couniot. VLSIC, page 1-2. IEEE, (2014)Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.D. Bol, C. Hocquet, D. Flandre, and J. Legat. ISCAS, page 1484-1487. IEEE, (2010)Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits.C. Gimeno, D. Bol, and D. Flandre. IEEE Trans. VLSI Syst., 26 (9): 1807-1811 (2018)A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS.C. Frenkel, M. Lefebvre, J. Legat, and D. Bol. IEEE Trans. Biomed. Circuits and Systems, 13 (1): 145-158 (2019)Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI.C. Gimeno, D. Flandre, and D. Bol. LASCAS, page 1-4. IEEE, (2018)Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors.P. Xu, D. Flandre, and D. Bol. A-SSCC, page 107-110. IEEE, (2018)A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm with 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs.M. Lefebvre, and D. Bol. CoRR, (2022)Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.D. Bol, I. Hassoune, D. Levacq, D. Flandre, and J. Legat. Multiple-Valued Logic and Soft Computing, 13 (1-2): 61-78 (2007)

PUMA

Disambiguation of "Bol, David"