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Integrated Analysis of Power and Performance for Pipelined Microprocessors., , , , , , and . IEEE Trans. Computers, 53 (8): 1004-1016 (2004)Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance., and . IEEE Trans. Computers, 36 (7): 859-875 (1987)Innovation or Notoriety?. IEEE Micro, 27 (4): 62-64 (2007)Guest Editor's Introduction: Existential Architectures: The Metaphysics of Computer Design.. IEEE Micro, 28 (6): 4-6 (2008)Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth.. HPCA, page 201-201. IEEE Computer Society, (2006)The End of Scaling? Revolutions in Technology and Microarchitecture as We Pass the 90 Nanometer Node.. ISCA, page 128. IEEE Computer Society, (2006)Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication., , , , and . MICRO, page 285-297. IEEE Computer Society, (2018)Cache miss behavior: is it sqrt(2)?, , , and . Conf. Computing Frontiers, page 313-320. ACM, (2006)Early-Stage Definition of LPX: A Low Power Issue-Execute Processor., , , , , , , , , and 6 other author(s). PACS, volume 2325 of Lecture Notes in Computer Science, page 1-17. Springer, (2002)Is 3D chip technology the next growth engine for performance improvement?, and . IBM Journal of Research and Development, 52 (6): 541-552 (2008)