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A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation.

, , , , , and . IEEE Trans. VLSI Syst., 18 (1): 29-38 (2010)

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Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design., , , , , , , and . DELTA, page 333-340. IEEE Computer Society, (2004)A VLSI System Architecture for Optical Flow Computation., , and . ISCAS, page 357-360. IEEE, (2009)A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing., and . ISVLSI, page 329-334. IEEE Computer Society, (2008)Variation Aware Timing Based Placement Using Fuzzy Programming., and . ISQED, page 327-332. IEEE Computer Society, (2007)Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition., and . IEEE Trans. Computers, 55 (12): 1523-1535 (2006)A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing., , and . IEEE Trans. VLSI Syst., 16 (8): 975-984 (2008)A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection., and . ISVLSI, page 180-185. IEEE Computer Society, (2005)Dynamic clock stretching for variation compensation in VLSI circuit design., , and . JETC, 8 (3): 16:1-16:13 (2012)An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition., and . VLSI Design, page 393-398. IEEE Computer Society, (2006)A novel approach for variation aware power minimization during gate sizing., , and . ISLPED, page 174-179. ACM, (2006)