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A design flow for linear-phase fixed-point FIR filters: from the NPRM specifications to a VHDL code., , , , and . ISCAS (4), page 277-280. IEEE, (2003)The design of asymmetrical square-root pulse-shaping filters with wide eye-openings., and . ISCAS, page 2665-2668. IEEE, (2008)Hardware Simplification to the Delta Path in a MASH 111 Delta-Sigma Modulator., and . IEEE Trans. on Circuits and Systems, 56-II (4): 270-274 (2009)A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM., , , and . IEEE Trans. VLSI Syst., 24 (1): 17-25 (2016)The Design of Square-Root-Raised-Cosine FIR Filters by an Iterative Technique.. IEICE Transactions, 90-A (1): 241-248 (2007)A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm., , , and . ISPACS, page 338-342. IEEE, (2012)Iterative learning of model reference adaptive controller for uncertain nonlinear systems with only output measurement., and . Automatica, 40 (5): 855-864 (2004)Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space., , and . IEEE Trans. on Circuits and Systems, 61-I (1): 202-212 (2014)Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line., , , and . IEEE Trans. VLSI Syst., 23 (3): 567-574 (2015)Fuzzy system-based adaptive iterative learning control for nonlinear plants with initial state errors., , and . IEEE Trans. Fuzzy Systems, 12 (5): 724-732 (2004)