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RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAs., , , , and . ReCoSoC, page 1-8. IEEE, (2012)Block cache for embedded systems., and . ASP-DAC, page 322-327. IEEE, (2008)RIVER: Reconfigurable Flow and Fabric for Real-Time Signal Processing on FPGAs., , and . TRETS, 7 (3): 24:1-24:16 (2014)RIVER: Reconfigurable Pre-Synthesized-Streaming Architecture for Signal Processing on FPGAs., , , , and . IPDPS Workshops, page 397-400. IEEE Computer Society, (2012)Reconciling application power control and operating systems for optimal power and performance., , , , , and . ReCoSoC, page 1-8. IEEE, (2013)Instruction Hints for Super Efficient Data Caches., , and . ICCS (2), volume 5545 of Lecture Notes in Computer Science, page 677-685. Springer, (2009)Automatic parallelization, performance predictability and power control for mobile-applications., , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2013)Fair Access to External Memory for Chip-multiprocessor., , , , and . IPDPS Workshops, page 300-305. IEEE Computer Society, (2012)Annotatable systrace: an extended Linux ftrace for tracing a parallelized program., , , , , , and . SEPS@SPLASH, page 21-25. ACM, (2015)ALPS: A Methodology for Application-Level Communication Characterization of Parsec 2.1., , and . ICCS, volume 4 of Procedia Computer Science, page 2086-2095. Elsevier, (2011)