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Disambiguation of "Mizuno, Masayuki"

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An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing.

, , , , , , , and . J. Solid-State Circuits, 45 (10): 2057-2065 (2010)

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Other publications of authors with the same name

A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery., , , , , and . ISSCC, page 192-193. IEEE, (2009)Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing., , , , , , , and . ISSCC, page 470-471. IEEE, (2009)LAGS System Using Data/Instruction Grain Power Control., , , , , , and . ISSCC, page 66-587. IEEE, (2007)A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect., , and . ISSCC, page 192-193. IEEE, (2010)A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors., , , , , , , , and . J. Solid-State Circuits, 45 (1): 15-22 (2010)An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing., , , , , , , and . J. Solid-State Circuits, 45 (10): 2057-2065 (2010)A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery., , , , , and . J. Solid-State Circuits, 44 (12): 3560-3567 (2009)A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests., , and . IEICE Transactions, 94-C (1): 102-109 (2011)The numerical analysis of mass evacuation in Taipei 101 with control volume model., and . Simulation Modelling Practice and Theory, (2019)Formal Verifications of Call-by-Need and Call-by-Name Evaluations with Mutual Recursion., and . APLAS, volume 11893 of Lecture Notes in Computer Science, page 181-201. Springer, (2019)