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Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow., , , , , , , and . IEEE Trans. VLSI Syst., 21 (5): 807-820 (2013)Framework for statistical design of a flip-flop., , , and . ICECS, page 679-682. IEEE, (2009)A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs., , , , and . IDT, page 13-17. IEEE, (2010)A statistical yield optimization framework for interconnect in double patterning lithography., and . Microelectronics Journal, 42 (11): 1231-1238 (2011)An electrical-aware parametric DFM solution for analog circuits., , , , , , , and . IDT, page 68-73. IEEE, (2011)High performance electrical driven hotspot detection solution for full chip design using a novel device parameter matching technique., , , , , and . ISQED, page 223-227. IEEE, (2012)Litho-Friendly Decomposition Method for Self-Aligned Double Patterning., , and . IEEE Trans. VLSI Syst., 21 (8): 1469-1480 (2013)RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO2/Hf 1T1R RRAM Memory Cell., , and . ACM Great Lakes Symposium on VLSI, page 227-232. ACM, (2016)Self-aligned double patterning (SADP) layout decomposition., , and . ISQED, page 103-109. IEEE, (2011)Schematic-driven physical verification: Fully automated solution for analog IC design., , , , , , and . SoCC, page 260-264. IEEE, (2012)