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Disambiguation of "Harutyunyan, Gurgen"

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Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.

, , , , , , and . ITC, page 1-10. IEEE, (2018)

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Other publications of authors with the same name

Fault modeling and test algorithm creation strategy for FinFET-based memories., , , and . VTS, page 1-6. IEEE Computer Society, (2014)Advanced Uniformed Test Approach For Automotive SoCs., , , , , and . ITC, page 1-10. IEEE, (2018)Extending fault periodicity table for testing external memory faults.. EWDTS, page 1-4. IEEE, (2016)Securing test infrastructure of system-on-chips., , , and . EWDTS, page 1-4. IEEE, (2016)Innovative Practices on In-System Test and Reliability of Memories., , , , , , , , , and 2 other author(s). VTS, page 1. IEEE, (2019)Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs., , , , and . ITC, page 1-6. IEEE, (2018)An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters., , , , and . EWDTS, page 1-4. IEEE Computer Society, (2013)Impact of process variations on read failures in SRAMs., , , and . EWDTS, page 1-4. IEEE Computer Society, (2013)Case Study and Advanced Functional Safety Solution for Automotive SoCs., and . ITC, page 1-8. IEEE, (2018)Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (3): 562-575 (2019)