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Disambiguation of "O'Mahony, Frank"

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Varactor-based signal restoration for near-speed-of-light surfing global interconnect.

, , , , and . CICC, page 1-4. IEEE, (2010)

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Lukas Frank University of Stuttgart

Daniel Frank University of Stuttgart

Frank Scheiner University of Stuttgart

Apl. Prof. Dr. Frank Kern University of Stuttgart

Univ. -Prof. Dr. Frank Leymann University of Stuttgart

 

Other publications of authors with the same name

Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver., , , , , , , , and . IEEE Trans. on Circuits and Systems, 56-I (8): 1818-1829 (2009)A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS., , , , and . VLSIC, page 1-2. IEEE, (2014)10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)Design considerations for low-power receiver front-end in high-speed data links., , , , and . CICC, page 1-8. IEEE, (2013)A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 57 (1): 6-20 (2022)EP3: Innovating on the tapeout treadmill., and . ISSCC, page 1. IEEE, (2015)An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements., , , and . J. Solid-State Circuits, 50 (7): 1711-1721 (2015)A low-power, 20-Gb/s continuous-time adaptive passive equalizer., , , and . ISCAS (2), page 920-923. IEEE, (2005)A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET., , , , , , , , , and . J. Solid-State Circuits, 54 (1): 29-42 (2019)Design of a 10GHz clock distribution network using coupled standing-wave oscillators., , , and . DAC, page 682-687. ACM, (2003)