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Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches.

, , , , and . European Test Symposium, page 13-18. IEEE Computer Society, (2011)

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New High-Speed Multioutput Carry Look-Ahead Adders., , and . IEEE Trans. on Circuits and Systems, 60-II (10): 667-671 (2013)A Design Technique for Energy Reduction in NORA CMOS Logic., , , and . IEEE Trans. on Circuits and Systems, 53-I (12): 2647-2655 (2006)A Robust and Reconfigurable Multi-mode Power Gating Architecture., , , and . VLSI Design, page 280-285. IEEE Computer Society, (2011)Low power scan by partitioning and scan hold., and . DDECS, page 262-265. IEEE, (2012)Timing Error Detection and Correction by Time Dilation., , and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 271-285. Springer, (2008)A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism., , , and . ICECS, page 692-695. IEEE, (2006)Cost and power efficient timing error tolerance in flip-flop based microprocessor cores., , and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)NBTI aging tolerance in pipeline based designs NBTI., , and . IOLTS, page 31-36. IEEE, (2013)Timing error tolerance in nanometer ICs., , and . IOLTS, page 283-288. IEEE Computer Society, (2010)A low power NORA circuit design technique based on charge recycling., , , and . ICECS, page 224-227. IEEE, (2003)