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OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis., , , , , and . Journal of Systems Architecture - Embedded Systems Design, 54 (11): 1019-1029 (2008)An accurate power estimation model for low-power hierarchical-architecture SRAMs., and . VLSI-SoC, page 144-149. IEEE, (2013)A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling., , , , , and . SoCC, page 271-274. IEEE, (2006)Design of a Pareto-optimization environment and its application to motion estimation., , and . MMSP, page 838-843. IEEE Signal Processing Society, (2008)Carry-save architectures for high-speed digital signal processing.. VLSI Signal Processing, 3 (1-2): 121-140 (1991)A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights., and . ESANN, (2012)A radix-4 single-precision floating point divider based on digit set interleaving., and . ISCAS, page 709-712. IEEE, (2010)Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations., , , , , , , and . ACM Comput. Surv., 47 (3): 38:1-38:33 (2015)Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets., , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 484-493. Springer, (2004)ASIP-eFPGA Architecture for Multioperable GNSS Receivers., , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 136-145. Springer, (2008)