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Adaptive FPGAs: High-Level Architecture and a Synthesis Method., , and . FPL, page 1-8. IEEE, (2006)Post-Placement BDD-Based Decomposition for FPGAs., , and . FPL, page 31-38. IEEE, (2005)Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow., , , and . IEEE Trans. VLSI Syst., 15 (8): 895-903 (2007)The Stratix™ 10 Highly Pipelined FPGA Architecture., , , , , , , , and . FPGA, page 159-168. ACM, (2016)Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow., , , and . SLIP, page 3-8. ACM, (2006)Incremental retiming for FPGA physical synthesis., , and . DAC, page 433-438. ACM, (2005)Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (11): 2331-2340 (2006)Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs., , , and . ICCAD, page 135-142. ACM, (2006)Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 232-241. Springer, (2002)Two-stage physical synthesis for FPGAs., , and . CICC, page 171-178. IEEE, (2005)