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Disambiguation of "Sekine, Toshikazu"

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An estimation method for the 3 port S-parameters with 1 port measurements.

, , , and . ECCTD, page 1-4. IEEE, (2013)

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Other publications of authors with the same name

Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology., , and . ECCTD, page 1-4. IEEE, (2013)Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design., , and . IET Circuits, Devices & Systems, 9 (5): 362-369 (2015)Two phase clocked subthreshold adiabatic logic circuit., , and . IEICE Electronic Express, 12 (20): 20150695 (2015)Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture., , and . ECCTD, page 1-4. IEEE, (2017)Low-power adiabatic SRAM., , and . ISPACS, page 1-4. IEEE, (2011)2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic., , , and . APCCAS, page 1484-1487. IEEE, (2006)Power dissipation analysis of memristor for low power integrated circuit applications., , and . APCCAS, page 627-630. IEEE, (2014)Two phase clocking subthreshold adiabatic logic., , and . ISCAS, page 598-601. IEEE, (2014)An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic., , and . ISCAS, page 826-829. IEEE, (2014)Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card., , and . ISPACS, page 1-5. IEEE, (2011)