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Functional decomposition with applications to FPGA synthesis.. Kluwer, (2001)SAT Modulo BDD -- A Combined Verification Approach for Incomplete Designs., , , , and . MBMV, page 107-116. Fraunhofer Verlag, (2010)Exploiting structure in an AIG based QBF solver., and . DATE, page 1596-1601. IEEE, (2009)Simple interpolants for linear arithmetic., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Checking Equivalence for Circuits Containing Incompletely Specified Boxes., and . ICCD, page 56-63. IEEE Computer Society, (2002)Fully Symbolic TCTL Model Checking for Incomplete Timed Systems., and . ECEASST, (2013)BDD minimization using symmetries., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (2): 81-100 (1999)Approximate Symbolic Model Checking for Incomplete Designs., and . FMCAD, volume 3312 of Lecture Notes in Computer Science, page 290-305. Springer, (2004)Task Variants with Different Scratchpad Memory Consumption in Multi-Task Environments., and . ARCS, volume 9637 of Lecture Notes in Computer Science, page 143-156. Springer, (2016)Exact State Set Representations in the Verification of Linear Hybrid Systems with Large Discrete State Space., , , , , , , , and . ATVA, volume 4762 of Lecture Notes in Computer Science, page 425-440. Springer, (2007)