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Disambiguation of "Davis, Robert I."

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Response-time analysis for fixed-priority systems with a write-back cache.

, , and . Real-Time Systems, 54 (4): 912-963 (2018)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

I. Steinwart

Kyle Davis University of Stuttgart

I. Dudic

Robert Henzel University of Stuttgart

Dr. rer. nat. Robert Seyfang University of Stuttgart

 

Other publications of authors with the same name

Choosing Task Periods to Minimise System Utilisation in Time Triggered Systems., and . Inf. Process. Lett., 58 (5): 223-229 (1996)Optimal Priority Assignment Algorithms for Probabilistic Real-Time Systems., , , , and . RTNS, page 129-138. (2011)Analysis of Checkpointing for Real-Time Systems., , and . Real-Time Systems, 20 (1): 83-102 (2001)FPSL, FPCL and FPZL schedulability analysis., and . Real-Time Systems, 48 (6): 750-788 (2012)Controller Area Network (CAN) schedulability analysis: Refuted, revisited and revised., , , and . Real-Time Systems, 35 (3): 239-272 (2007)Response-Time Analysis for Mixed Criticality Systems., , and . RTSS, page 34-43. IEEE Computer Society, (2011)Dual Priority Scheduling., and . RTSS, page 100-109. IEEE Computer Society, (1995)FPZL Schedulability Analysis., and . IEEE Real-Time and Embedded Technology and Applications Symposium, page 245-256. IEEE Computer Society, (2011)Integrating cache related pre-emption delay analysis into EDF scheduling., , , and . IEEE Real-Time and Embedded Technology and Applications Symposium, page 75-84. IEEE Computer Society, (2013)Guaranteeing timing constraints under shortest remaining processing time scheduling., , and . RTS, page 88-93. IEEE Computer Society, (1997)