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Disambiguation of "Kuh, Ernest S."

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Transient Simulation of Lossy Interconnect.

, and . DAC, page 81-86. (1992)

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S. Schumann

S. Seemann

Prof. Dr. -Ing. Ulrike Kuhlmann University of Stuttgart

Stiffness of Steel-Timber Dowel Connections : Experimental and Numerical Research, and . INTER Proceedings : Meeting 54, page 227-242. Karlsruhe, Timber Scientific Publishing, (2021)
Stiffness of Steel-Timber Dowel Connections : Experimental and Numerical Research, and . INTER Proceedings : Meeting 54, page 227-242. Karlsruhe, Timber Scientific Publishing, (2021)Imperfections of slender glulam beams, and . INTER Proceedings : Meeting 54, page 317-332. Karlsruhe, Timber Scientific Publishing, (2021)Analytical and numerical investigations on imperfection-sensitive timber members subjected to combined bending and axial compression, and . World Conference on Timber Engineering (WCTE 2021), 3, page 1982-1989. Red Hook, Curran Associates, Inc., (2021)

S. Wartzack

Boettinger S

 

Other publications of authors with the same name

Routing Region Definition and Ordering Scheme for Building-Block Layout., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 4 (3): 189-197 (1985)Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 6 (5): 828-837 (1987)Glitter: A Gridless Variable-Width Channel Router., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 5 (4): 459-465 (1986)A new performance-driven global routing algorithm for gate array., , and . VLSI, volume A-42 of IFIP Transactions, page 321-330. North-Holland, (1993)Design methodology of high performance on-chip global interconnect using terminated transmission-line., , , , , , , and . ISQED, page 451-458. IEEE Computer Society, (2009)SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits., , and . EURO-DAC, page 142-148. EEE Computer Society, (1991)TIGER: an efficient timing-driven global router for gate array and standard cell layout design., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (11): 1323-1331 (1997)Post global routing crosstalk synthesis., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (12): 1418-1430 (1997)A spacing algorithm for performance enhancement and cross-talk reduction., , and . ICCAD, page 697-702. IEEE Computer Society / ACM, (1993)Hierarchical placement for macrocells: a 'meet in the middle' approach., , , and . ICCAD, page 460-463. IEEE Computer Society, (1988)