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A Formal Approach to the Verification of Networks on Chip., , , and . EURASIP J. Emb. Sys., (2009)Synthesizable delay line architectures for digitally controlled voltage regulators., , , and . SoCC, page 72-77. IEEE, (2012)VHDL implementation of a power management algorithm for PV-battery system., , and . ICEAC, page 1-4. IEEE, (2015)Redundancy and ECC mechanisms to improve energy efficiency of on-die interconnects., and . ICEAC, page 1-6. IEEE, (2012)A Low Power CORDIC-Based Hardware Implementation of Izhikevich Neuron Model., , , , , and . NEWCAS, page 130-133. IEEE, (2018)A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study., , , and . NOCS, page 127-136. IEEE Computer Society, (2007)VHDL implementation of Maximum Power Point Tracking algorithms., , , and . ICECS, page 389-392. IEEE, (2013)Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing., , and . DDECS, page 221-224. IEEE Computer Society, (2010)Executable formal specification and validation of NoC communication infrastructures., , , and . SBCCI, page 176-181. ACM, (2008)TPQA: Three point quadrature approximation MPPT algorithm., , , and . ICECS, page 397-400. IEEE, (2013)