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Disambiguation of "Tupuri, Raghuram S."

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Timing Verification and Delay Test Generation for Hierarchical Designs.

, , and . VLSI Design, page 157-162. IEEE Computer Society, (2001)

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Other publications of authors with the same name

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits., , and . VLSI Design, page 521-526. IEEE Computer Society, (2008)A Comprehensive Fault Model for Deep Submicron Digital Circuits., , and . DELTA, page 360-364. IEEE Computer Society, (2002)A Novel Hierarchical Test Generation Method for Processors., and . VLSI Design, page 540-541. IEEE Computer Society, (1997)A Novel Functional Test Generation Method for Processors Using Commercial ATPG., and . ITC, page 743-752. IEEE Computer Society, (1997)Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor., , and . DAC, page 647-652. ACM Press, (1999)Timing Verification and Delay Test Generation for Hierarchical Designs., , and . VLSI Design, page 157-162. IEEE Computer Society, (2001)Hierarchical Test Generation for Systems On a Chip., , and . VLSI Design, page 198-. IEEE Computer Society, (2000)A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages., , , and . J. Electronic Testing, 19 (2): 149-160 (2003)Delay Constrained Register Transfer Level Dynamic Power Estimation., , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 36-46. Springer, (2006)Design Migration Across Technology - Making It Work., , , , , , and . VLSI Design, page 68-72. IEEE Computer Society, (1992)