Author of the publication

cycle and resistive DAC in 65nm CMOS.

H. Wei, C. Chan, U. Chio, S. Sin, S. U., R. Martins, and F. Maloberti. ISSCC, page 188-190. IEEE, (2011)

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Simon Sailer University of Stuttgart

Dr. Cornelia Martina Sindermann University of Stuttgart

Oskar Wengrzyn University of Stuttgart

Ingeborg Wenger University of Stuttgart

Bhupender Kumar Saini University of Stuttgart

Other publications of authors with the same name

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.H. Wei, U. Chio, Y. Zhu, S. Sin, S. U, and R. da Silva Martins. APCCAS, page 1192-1195. IEEE, (2008)A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure.C. Chan, Y. Zhu, S. Sin, S. U, and R. Martins. VLSIC, page 86-87. IEEE, (2012)A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction.J. Zhong, Y. Zhu, C. Chan, S. Sin, S. U, and R. Martins. ESSCIRC, page 169-172. IEEE, (2016)Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_cm$ -Based Switching.D. Xing, Y. Zhu, C. Chan, S. Sin, F. Ye, J. Ren, S. U, and R. Martins. IEEE Trans. VLSI Syst., 25 (3): 1168-1172 (2017)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC.H. Wei, C. Chan, U. Chio, S. Sin, S. U., R. Martins, and F. Maloberti. J. Solid-State Circuits, 47 (11): 2763-2772 (2012)A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC.C. Chan, Y. Zhu, S. Sin, S. U, and R. Martins. J. Solid-State Circuits, 51 (2): 365-377 (2016)Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators.M. Huang, Y. Lu, S. Sin, S. U, R. Martins, and W. Ki. IEEE Trans. on Circuits and Systems, 63-II (9): 903-907 (2016)A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches.D. Feng, E. Bonizzoni, F. Maloberti, S. Sin, and R. Martins. IEEE Trans. on Circuits and Systems, 65-II (10): 1410-1414 (2018)A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.Y. Jiang, K. Wong, C. Cai, S. Sin, S. U, and R. Martins. APCCAS, page 1011-1014. IEEE, (2010)Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC.J. Liu, Y. Zhu, C. Chan, S. Sin, S. U, and R. da Silva Martins. IEEE Trans. VLSI Syst., 24 (7): 2603-2607 (2016)

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Disambiguation of "Sin, Sai-Weng"

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A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.

Please choose a person to relate this publication to

Simon Sailer University of Stuttgart

Dr. Cornelia Martina Sindermann University of Stuttgart

Oskar Wengrzyn University of Stuttgart

Ingeborg Wenger University of Stuttgart

Bhupender Kumar Saini University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Sin, Sai-Weng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.

Please choose a person to relate this publication to

Simon Sailer University of Stuttgart

Dr. Cornelia Martina Sindermann University of Stuttgart

Oskar Wengrzyn University of Stuttgart

Ingeborg Wenger University of Stuttgart

Bhupender Kumar Saini University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.